FIG. 1 is a circuit diagram illustrating an ECL (Emitter Coupled Logic) inverter/buffer circuit as an example of the electronic circuit to which the constant voltage generating circuit of the present invention can be applied.
The ECL inverter/buffer circuit has second and third npn bipolar transistors Q2 and Q3 whose emitters are connected together and which can function as a differential amplifier. The ECL inverter/buffer circuit also has load resistors RL, RL of the same resistance value arranged between the collectors of transistors Q2, Q3 and the supply part (supply rail) of the first power supply voltage V.sub.cc. In addition, the ECL inverter/buffer circuit has a first npn bipolar transistor Q1 used as a constant current source and a first resistor RE1 which are connected between the supply rail of the second power supply voltage V.sub.EE and the connection node of the emitters of transistors Q2 and Q3.
The ECL inverter/buffer circuit has a fourth npn bipolar transistor Q4, which acts as an output buffer, and whose collector is connected to the supply rail of the first power supply voltage V.sub.CC. The first output signal at the collector of the second transistor Q2 is applied to the base of the fourth bipolar transistor. A sixth npn bipolar transistor Q6, which acts as a constant current source for transistor Q4, and a second resistor RE2 are connected between the emitter of transistor Q4 used as the output buffer and the supply rail of the second power supply voltage V.sub.EE.
The ECL inverter/buffer circuit also has a fifth npn bipolar transistor Q5, which acts as an output buffer, and is connected to the supply rail of the first power supply voltage V.sub.CC. The second output signal at the collector of the third transistor Q3 is applied to the base of the fifth bipolar transistor. A seventh npn bipolar transistor Q7, which acts as the constant current source of transistor Q5, and a third resistor RE3 are connected between the emitter of transistor Q5 used as the output buffer and the supply rail of the second power supply voltage V.sub.EE.
In the ECL inverter/buffer circuit shown in FIG. 1, a signal corresponding to the difference between the first input signal AY applied to the base of the second transistor Q2 and the second input signal AX applied to the base of the third transistor Q3 is output to the collectors of the second and third transistors Q2 and Q3. The output signals are applied to the bases of the fourth and fifth transistors Q4 and Q5 which are used as the output buffers. The final output signals X and Y are output from the emitters of said transistors Q4 and Q5, respectively.
In the ECL inverter/buffer circuits shown in FIG. 1, a control voltage (or reference voltage) V.sub.CS is applied to the bases of transistors Q1, Q6, and Q7 used as the constant current sources such that control currents I.sub.CS of equal value flow from said transistors Q1, Q6, and Q7 through resistors RE1-RE3, respectively.
In the ECL inverter/buffer circuits shown in FIG. 1, the first to the third resistors RE1-RE3 have the same resistance of R.sub.e.
The amount of current I.sub.CS flowing through transistors Q1, Q6, and Q7 is relatively large.
In the ECL inverter/buffer circuit shown in FIG. 1, there are three constant current sources. Consequently, the power consumption is V.sub.CC.times.I.sub.CS.times.3 (V.sub.CC is the value of the power supply voltage V.sub.CC, and I.sub.CS is the value of the control current I.sub.CS).
The control current I.sub.CS flowing through transistors Q1, Q6, and Q7 is defined by the following formula 1. EQU I.sub.CS =(V.sub.CS -V.sub.BE)/R.sub.e (1)
where V.sub.CS is the reference voltage (control voltage) applied to the bases of transistors Q1, Q6, and Q7; PA1 V.sub.BE is the base-emitter voltage (pn junction voltage) of transistors Q1, Q6, and Q7; and R.sub.e is the resistance of the first to third resistors RE1-RE3. PA1 where, V.sub.BE (Q11) is the base-emitter voltage of transistor Q11, PA1 V.sub.BE (Q12) is the base-emitter voltage of transistor Q12, PA1 I.sub.c1 is the current flowing through resistor RC1, PA1 I.sub.c2 is the current flowing through resistor RC2, PA1 T is the absolute temperature, PA1 k is Boltzmann's constant, and PA1 q is the charge on the electron. PA1 where, V.sub.BE (Q13) is the base-emitter voltage of transistor Q13 incorporated in buffer circuit BUF, PA1 V.sub.RC1 is the voltage across resistor RC1, PA1 R.sub.c1 is the resistance of resistor RC1, and PA1 R.sub.e is the resistance of resistor RE.
When the total power consumption of a logic integrated circuit (logic IC) formed by integrating many logic circuits including the ECL inverter/buffer circuit shown in the FIG. is calculated on the bases of the aforementioned current consumption, it is found that the power consumption of the entire IC chip is in the range of one to several watts. The surface temperature of the IC chip becomes high due to the heating caused by the current consumed.
In addition to finding an effective heat dissipation method to prevent the aforementioned heating problem, it is also necessary to find a means which can effectively prevent "thermal runaway," which will destroy the IC chip as a result of repeating the cycle in which the chip is heated by the current consumed, and which in turn further increases the current consumption.
In order to prevent thermal runaway, the temperature coefficient of control current I.sub.CS is preferrably to be negative. In formula 1, the temperature coefficient of the pn junction voltage V.sub.BE of the bipolar transistor is negative. It is usually -2 mV/.degree. C. Consequently, the temperature coefficient of control voltage V.sub.CS must be greater than -2 mV/.degree. C. It is also necessary to control the temperature coefficient of control voltage V.sub.CS in consideration of the temperature coefficients of resistors RE1-RE3. If the temperature coefficients of the resistors are negative, by adding these temperature coefficients, the temperature coefficient of control voltage V.sub.CS must have an even larger negative value. Also, it is preferred that [the temperature coefficient of the control voltage] be constant irrespective of the changes in the first and second power supply voltages V.sub.CC and V.sub.EE.
Based on the aforementioned point of view, a conventional constant voltage generating circuit (reference voltage generating circuit) used for generating the control voltage (reference voltage) applied to the bases of transistors Q1, Q6, and Q7 in the ECL inverter/buffer circuit shown in FIG. 1 or a voltage applied to another electronic circuit will be explained with reference to FIGS. 2 and 3.
The constant voltage generating circuit (reference voltage generating circuit) shown in FIG. 2 is a well-known constant voltage generating circuit called a bandgap reference circuit.
The bandgap reference-type constant voltage generating circuit has a reference current source circuit I.sub.ref, an npn bipolar transistor Q11, an npn bipolar transistor Q12 whose base is connected to its collector and can function as a pn junction diode, as well as resistors RC1, RC2, and RE. The constant voltage generating circuit also has a buffer circuit BUF, which is an amplifier circuit with a gain of 1 and has an npn bipolar transistor Q13 (not shown in the FIG.) incorporated.
As can be seen from the FIG., a current-mirror constant-current source is formed by transistors Q11 and Q12.
In the constant voltage generating circuit shown in FIG. 2, a voltage V.sub.CS of prescribed value can be output from buffer circuit BUF by setting the values of resistors RC1, RC2, and RE appropriately.
In the constant voltage generating circuit shown in FIG. 2, it is believed that transistors Q1 and Q12 used for forming the current mirror type current source circuit have the same characteristics. Consequently, the voltage V.sub.RE across resistor RE can be expressed by the following formula. EQU V.sub.RE =V.sub.BE (Q12)-V.sub.BE (Q11)=(kT/q).times.1n(I.sub.c2 /I.sub.c1) (2)
The voltage V.sub.CS output from buffer circuit BUF is expressed by the following formula. ##EQU1##
The base-emitter voltage (pn junction voltage) V.sub.BE (Q13) of transistor Q13 incorporated in buffer circuit BUF has a temperature coefficient of about -2 mV/.degree. C. The temperature coefficient of control voltage V.sub.CS becomes 0when (RC1/RE).multidot.(kT/q).multidot.1n(I.sub.c2 /I.sub.c1)=23.2, where Boltzmann's constant k=1.38.times.10.sup.-23 (J/K) and electronic charge q=1.6.times.10.sup.-19 (C) have been substituted into the formula. If V.sub.BE (Q13) is assumed to be 0.8 V and the values of the resistors are selected appropriately at 25.degree. C., the output voltage V.sub.CS becomes 1.25 V, which is close to the bandgap value of silicon (1.2 V).
The bandgap reference type constant voltage generating circuit shown in FIG. 2 is not affected by the change in the first power supply voltage V.sub.CC (has no voltage dependence) and is able to control the temperature coefficient as described above. This is an advantage.
The constant voltage generating circuit shown in FIG. 3 has a reference current source circuit I.sub.ref, a diode DX using the pn junction of a transistor formed by connecting the base to the collector of bipolar transistor QX, and an amplifier circuit AMP.
The amplifier circuit AMP has an input resistorR1, a negative feedback resistor R2, and an amplifier QAMP made up of a bipolar transistor.
In this constant voltage generating circuit, the pn junction voltage V.sub.BE of transistor QX is yamplified by (R1+R2)/R1 using amplifier circuit AMP, and the amplified voltage is output as output voltage V.sub.CS.
When the voltage drop of the pn junction of transistor QX in the forward direction, that is, the base-emitter voltage V.sub.BE of the transistor as well as the values of resistors R1 and R2 are set appropriately, like that of the bandgap reference circuit, the output voltage V.sub.CS can also be set in the range of about 1.25-1.30 V.
In the ECL inverter/buffer circuit shown in FIG. 1, the temperature coefficient of the base-emitter voltage V.sub.BE of the bipolar transistor, that is, the voltage drop V.sub.BE of the pn junction of the transistor in the forward direction is about -2 mV/.degree. C. When the ECL inverter/buffer circuit is fabricated as an IC circuit, resistors RE1-RE3 are formed as diffusion resistors or polysilicon resistors. Polysilicon resistors have a negative temperature coefficient.
When resistors RE1-RE3 are made of polysilicon and the constant voltage generating circuit used for generating control voltage V.sub.CS exhibits a positive temperature coefficient, the temperature coefficient of control current I.sub.CS becomes positive. As a result, the IC chip might be destroyed as a result of thermal runaway.
In the constant voltage generating circuit shown in FIG. 2, output voltage V.sub.CS is defined by formula 3, that is, V.sub.CS =V.sub.BE (Q13)+.alpha.(kT/q). Since kT/q indicates a positive temperature coefficient, the temperature coefficient of output voltage V.sub.CS cannot be a negative temperature coefficient greater than that of voltage V.sub.BE, that is, the pn junction voltage. Consequently, the aforementioned purpose of obtaining a negative temperature coefficient greater than that of V.sub.BE cannot be realized by the constant voltage generating circuit shown in FIG. 2.
In the constant voltage generating circuit shown in FIG. 3, even when it is assumed that reference current source circuit I.sub.ref is independent of the temperature characteristics, since the temperature coefficient of output voltage V.sub.CS is defined as the value obtained by amplifying the temperature coefficient of the pn junction voltage V.sub.BE of the transistor by the gain of amplifier circuit AMP, that is, (R1+R2)/R1, the temperature coefficient of output voltage V.sub.CS is determined solely by the value of output voltage V.sub.CS. This is a disadvantage.
For example, when output voltage V.sub.CS is 1.3 V, the temperature coefficient of output voltage V.sub.CS cannot be defined as, say, -2.4 mV/.degree. C. independent of the voltage value. When output voltage V.sub.CS is 1.3 V, the temperature coefficient is determined by the voltage value at that time. This is a disadvantage.
Some conventional control (output) output voltage V.sub.CS generating circuits used for the ECL inverter/buffer circuit shown in FIG. 1 are explained with reference to FIGS. 2 and 3. These constant voltage generating circuits can be used for other types of electronic circuits in addition to the circuit shown in FIG. 1. However, the same problem concerned with the aforementioned thermal runaway also occurs when they are used for other types of electronic circuits.
One purpose of the present invention is to provide a constant voltage generating circuit which can control the temperature dependence to prevent thermal runaway and is able to generate a constant voltage in spite of the change in the power supply voltage.
Another purpose of the present invention is to provide a constant voltage generating circuit which can generate a voltage with a prescribed value.
Yet another purpose of the present invention is to provide a constant voltage generating circuit which has the aforementioned properties and can be incorporated with electronic circuits, preferably, semiconductor integrated circuits.